Analysis of conditional resource sharing using a guard-based control representation

Optimization of hardware resources for conditional data-flow graph behavior is particularly important when conditional behavior occurs in cyclic loops and maximiza-tion of throughput is desired. In this paper, an exact and efficient conditional resource sharing analysis using a guard-based control representation is presented. The analysis is transparent to a scheduler implementation. The proposed technique systematically handles complex conditional resource sharing for cases when folded (software pipelined) loops include conditional behavior within the loop body.